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The Unit Cell Design

The Wafer/Die Settings

Matching Existing Die

Generating the Array
with GDS-SR

Plating on RDL/UBM

Clip to a Round Boundary

Knocking Out Openings

Dropping in the FIDS

Solder Stencil Issues


Wafer and Die Setttings

    In this example we are working with:

    a) a 200 mm diameter wafer

    b) an exclusion zone of 2.5 mm at all edges of the wafer

    c) a die of 3000 x 3000 um with a street width of 50 um

You can see a simple drawing of where we are starting below:

Next - Notes on matching the existing pattern on the wafer and openings ....

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