A TraceDef is named because it represents a circuit trace contained inside of a PackageDef. One probably won't find it when defining a die or substrate but possibly when building a cover cell for a flipchip. Its definition is as follows.

(TraceDef
 (Name 'T-1')
 (Polyline
  0 0 10
  200 0 10 ARC 0.4142
  400 200 10
  400 400 10
 )
)

This introduces the Polyline definition, which is similar to the Polygon definition. A Polyline describes a possibly curved path, consisting of a series of vertices with associated width. It can be used to define circuit traces, wires and has a variety of other uses. Each vertex is followed by the width of the polyline at that vertex. The polyline need not revisit its first vertex.

Macro

A Macro is simply an instance of a PackageDef embedded inside another PackageDef. As mentioned earlier, Macros can be nested as needed. A repeated piece of circuitry may make up a larger Macro, which in turn may appear several times in a package definition. The Macro definition is hence very simple.

(Macro
 (Name 'M-1')
 (PackageDef 'LOGIC-1')
 (Location -1000 200)
 (Rotation 0)
)

We expect that macros will be most useful when designing the layout of a flip chip.