The Netex-G library (netexglib) is a library implementation for OEMs who whish to use NETEX-G as the front end to a simulation or 3D modeling engine. Most of the arguments in netexglib are equivalent to the arguments found in the command line version of Netex-g.
implemented in v1.14 (04/08/2019)
For simulation OEMs who would prefer to deal with STEP or parasolids 3D formats (instead of Artwork's ASCII or 3Di output formats) we have added these two new outputs.
Controlling these outputs adds a number of arguments/parameters which are documented below.
To generate STEP Output use the argument:
-outtype:step
There are a number of arguments that can "flavor" the STEP output. These must be surrounded by:
-bgn_step_args [-fea] <arg1> <arg2> <arg3> ... -end_step_args
FFF vs FEA
The STEP output is separated into two main types - a simple STEP we call FFF (form, fit, function) and a STEP that requires a number of additional operations which makes it better for FEA, which we call, naturally, FEA. The default is FFF. There are very few arguments associated with FFF output.
FFF Arguments
Assuming you do not have the -fea option as the first one in the list, then the remaining options are few:
Type of STEP
There are a great many flavors of STEP. The two that are supported are STEP AP203 and STEP AP214. The default output is 203 but we recommend you use AP214 as this version supports color.-ap214
Union Operation
The user can request that the program unionize any solid bodies who share the same Z-extrusion value (and who are members of the same "part").
-unionize
STEP Units
To control the units of the STEP file use
-units:in or -units:mm
FEA Arguments
Assuming you wish to output an FEA optimized STEP file, then your first argument must be -fea. This can be followed by a large number of arguments that control different operations.
You can also follow -fea with -ap214, -units or even -unionize. However we don't recommend -unionize with FEA output because it may remove information that some FEA options require.
Controlling the Hierarchy of the STEP File
Use the -alternate: attribute argument to control how the STEP file is organized. The most common is to sort by layer - the incoming conductor and dielectric layers found in a PCB.
-alternate:LAYER
Other attributes you can use to organize the STEP data are:
COLOR
HISTORY
LAYER_TYPE
NET
NET_PINS
OBJECT
STACK_UP
Sorting Vias by Diameter
One of our clients wanted to replace vias with an equivalent electrical model during simulation. This saved lots of FEA on the vias. However to do this, they needed to organize the vias by diameter, since different diameter vias require a different model. This option separates the vias by diameter.
-via_sort
Merging Vias
When the library generates vias, it produces a separate via for each PCB layer. (i.e. one via passing through the conductor, another passing through the dielectric and so on.) Modeling the vias in this manner can cause the mesher and simulator to do a lot of extra and unnecessary work. (The library does assign each of these stacked via sections a common ID. To merge all these vias sharing a common ID into a single "column" use the option:
-via_merge
Duplicate Pin Conductor Removal
When reading the ASCII file produced by NETEX-G, one finds that at each pin location there are two conductors produced - one from the conductor layer information in ODB++ and a second one from the component placement footprint. While this duplication is not an issue for outputs such as Gerber, it will produce in 3D, two solid bodies that intersect -- which is generally forbidden.
Hence the argument -remove_pins can be used which identifies the geometry associated with a component placement (by its attribute) and deletes it prior to conversion to 3Di or STEP.
-remove_pins
Expanding the Dielectric Boundary
If the simulator requires dielectric bodies to be generated, the boundary of all the dielectric bodies is defined by an outline or profile. However when the user wants the library to also produce what we call negative dielectric, the need arises to slightly increase the dielectric bounding box so that is extends very slightly past the conductor data. This is due to the manner in which we compute the negative dielectric. Hence the need for this directive which is accompanied by the expansion value d.
-expand_dielectric:<d>
Generate Negative Dielectric
Since each conductor layer and each dielectric layer occupies a unique range of Z-values, there are air gaps in each conductor layer where no conductor is present. In a real PCB, the combination of pressure and temperature during the bonding of the layers causes dielectric to flow into these regions.
In order to generate a 3D representation of this, we generate what we call - for lack of a better word, negative dielectric. You can think of it as the difference generated by subtracting the conductors in a given layer from the dielectric boundary.
When this option is invoked, the user must also invoke -expand_dielectic.
-negative_dielectric
Set Number of Via Sides
The number of sides present on the 3D model of a via may be 1 (i.e. the via top/bottom surface is modeled using a circle) or it may be determined by a parameter set within the ODB converter. However this value may still not be what the user desires. This command overrides the via's definition and uses the number of sides specified.
This feature was added at the request of one of our simulation partners who did not want to expend a lot of mesh and compute cycles on vias.
-via_sides:<sides>
Drill a Hole Through Conductor/Dielectric Where a Via Passes Through
If you want to build a 3D model where the vias do not generate a solid body interference with the conductors or dielectrics, then use this argument. The program will "drill" a hole where each via passes through the conductor or dielectric.
Note: it is critical that the hole and the via have perfectly matching faces so that there is neither a tiny air gap nor any solid body interference.
-via_drills
Via with Drill Hole
The standard model for a via is a solid cylinder. A more realistic via would be modeled as a thin shell -- essentially the solid cylinder with a hole drilled through it. This argument instructs the program to generate a cylindrical shell with a user specified wall thickness.
Note that this increases the complexity of the 3D model as it needs surfaces on both the inside and outside of the via.
-via_wall:<thickness>
Plug the Via Hole
If the user chooses to model vias with holes drilled through, he may also want the via "plugged" with a separate material. This option generates a solid body inside of each via. This is a more accurate model of a physical via which has been plugged with solder.
-via_plugs