Merging Via Arrays

VDD and VSS nets are the largest nets (in terms of both area and number of polygons) you will find in an IC layout. So any field simulator will already be stressed to the limit when attempting to analyze the current flow through these nets.

The conductors for VSS/VDD are generally much wider than those used for signals since they must carry high currents with very small voltage drops. When dropping from one layer to a lower one a via must be used. But instead of using a large via proportional to the width of the conductor, you will find that an array of small vias is used. There are process related issues that require this approach.

comparison of via for signal and VSS/VDD trace

Such a large array of vias will force the field simulator to generate a very complex mesh and the simulator will converge extremely slowly towards a solution.


Merging the Array into a Single Large Via

What we would like to do is to merge the arrayed vias into a single large via. While this will introduce some error into our field simulator, the size of the error has been simulated and found to be negligble if the proper adjustments are made to account for the difference in conductor density between the arrayed vias and the solid via.


single large via in power/ground trace

Our simulation will run faster if a single large via replaces the array.



How to Merge the Vias

We found that the via arrays could be safely merged into a single large rectangle by using the following flow:

flow for merging via arrays into a single large rectangle.

    1) GDSFILT is used to separate the via layers from the "trace" layers. If we skip this step then we will short out lots of conductor traces and that is not our intent.

    2) QCKBOOL is used to size up the via layers. The amount of sizing depends on the via spacing. We found a sizing of 3 um is enough to insure all vias in an array overlap but that adjacent arrays do not overlap.

    3) QCKBOOL is used to unionize the via layers and to then size the resulting large rectangle down again by the same amount we originally sized up. This leaves us a rectangle that exactly covers the array's extents.

    4) GDSFILT is used to combine the new via layers with the trace layers. The resulting GDSII file is now much much smaller and can be sent to the simulation software.


To show how this works at the geometric level we have drawn a simplified array (3x3 instead of 10x10) below.

via merge geometric illustration

    a) An 3x3 array of 2 um vias over a wide VDD/VSS trace. We've simplified the array for illustrative purposes. In a real IC the array would have anywhere from 100 to 900 members.

    b) vias are sized up by 3.1 um on all sides using Artwork's Qckbool program. This causes the individual members of the array to overlap slightly.

    c) The UNION operation (using QckBool) merges the overlapping vias into a single large rectangle. However you can see that it now "leaks" out beyond its orginial extents.

    d) The large rectangle is sized back down by 3.1 um. It now exactly represents the original extents of the via array. This is what will be sent to the simulation software.


Summary of Via Merging Flow

This layer separation, sizing up/down and layer recombination operation is performed using a script to control both GDSFILT and Qckbool; it runs relatively quickly even on very large files since the data in the array layers is quite simple. To give you an idea of data size reduction, we ran this operation on a GDSII file of a VSS net (only 1/9 of the chip) that was 67 MB in size (flat file). After the via merging the resulting GDSII file was 670KB in size -- a reduction factor of 100


Via Merging Must be Done Net-by-Net

One important detail has been glossed over -- the via merging process must be done on a net by net basis -- that is, if you are extracting both VDD and VSS for analysis, you must produce two independent GDSII files from NETEX - one with only VDD data and one with only VSS data.

This is because during the sizing process, the GDSII hierarchy is flattened and any net information embedded into the hierarhcy is lost (since nets are stored in their own GDSII structure ...)

This is not a major roadblock - it only makes your script a bit more complex since after you have merged the vias for each net file, you must then call GDSFILT one more time to merge the two NET files into a single output containig both nets.



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