Most chip designs have many vias - often a single crossing of metal with another metal layer may use many tiny vias rather than a single large one. In order to accelerate the performance on large GDSII files NETEX makes a couple of assumptions about the use of vias in a design.

1. that vias are rectangular



2. that the center of the via can be used to determine if the via is under a piece of metal. (i.e. we assume that a via is placed such that it’s center lies under and over the metal pieces it connects.)

Via at Left - our assumptions would not connect the two layers of metal.

Via at Right - we assume that the via center lies under and over the two pieces of metal.

These assumption greatly reduce both the memory required to store the vias and the computation required to determine whether a piece of metal lies over a via.