Designers of optical components for the telecom industry take advantage of the existing mask and etching infrastructure developed by the IC industry in order to produce their fine geometry structures. However they frequently run into problems that were not anticipated because there are very important differences between optical layouts and IC layouts.

This article describes those differences, how those differences can cause problems in the masks used to define the structures and how one can work around such problems.

Our paper discusses the problems encountered when converting CAD data produced in AutoCAD (or equivalent layout software) which is converted to mask data.

Often there are two conversions -- first from the AutoCAD database into the IC industry standard GDSII stream database -- then into a specific mask making machine data format such as MEBEs. The machine that writes the mask, typically an electron beam writer manufactured by ETEC, reads the MEBEs database.

Optical structures such as waveguides, couplers and switches are characterized by:

1. Narrow channels on the order of 1 um
2. Can be very long - up to 10,000 to 100,000 um
3. Width or Spacing between guides changes very gradually
4. No sharp steps or bends are allowed
5. Design data often described using curves.

When optical designers hear about the IC industry's ability to image sub micron lines they assume that their structures should also be easy to image. However, some of their requirements don't align with the IC processes. For example:

IC CAD data is grid based. Some years ago the grid value was 1.0 um. It has dropped steadily to 0.5 um, 0.25 um and even below that for the tightest processes. However in the IC world there is no need to smoothly change the width of a line -- So these tight resolutions apply only for parallel and very short lines.

IC CAD data is never described using arcs or splines. In fact, even most lines are only drawn at 90 degrees. CAD data for optical structures that uses arcs must be reduced into line segments. This can be a major source of errors if the conversion rules and limits are not understood.

One way that IC designers get such fine lines is to use a reduction lens during the imaging process. This means that their masks are actually 4X or even 10X the actual linewidth on the wafer. It turns out that many optical components cannot be imaged in this fashion -- there is an upper limit to the size of a single die when reduced like this and many optical components exceed this limit. Therefore they must be imaged at 1:1.